Close category search window
 

Test cost reduction using partitioned grid random access scan

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Dong Hyun Baik ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Saluja, K.K.

The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester channels.

Published in:
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

Date of Conference: 3-7 Jan. 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.