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This paper is devoted to the design and implementation of high speed, low power, low voltage flash analog-to-digital convertors (ADC). A 4-bit flash ADC, with a maximum acquisition speed of 400 MHz, is implemented in a 1.8 V analog supply voltage. The large input signal dynamic range is handled using a fast switching common mode jump circuit, implemented with complementary pass transistors, which eliminates the need for high input-common-mode-range (ICMR) preamplifier based comparators. The measured INL/DNL is 0.4/1.1 LSB. The signal-to-noise-plus-distortion ratio (SNDR) obtained at 12.5 MHz input is 21.25 dB. The spurious-free dynamic range (SFDR) is 27.6 dB and power consumption is only 30 mW. Design and simulations results are presented in dual-poly 0.18μ pure digital CMOS technology.
Date of Conference: 3-7 Jan. 2006