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Design challenges for high performance nanotechnology

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2 Author(s)
Debnath, G. ; Intel Corp., Hillsboro, OR, USA ; Thadikaran, P.

Summary form only for tutorial. This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nanotechnology. The focus is on design challenges that are experienced in microprocessor designs. It captures the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification. It describes the requirements to meet power, timing, physical dimension and process portability goals with nanotechnology. It also addresses the pre and post silicon verification difficulties that have a direct impact on taking the product to market.

Published in:

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

Date of Conference:

3-7 Jan. 2006

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