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This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex IP blocks and high-speed buses and interconnection networks. This tutorial addresses the following emerging challenges: architectural exploration, HW/SW co-design, complex control and concurrency, correctness and verification, timing closure, and low-power. The tutorial focuses on language facilities and synthesis techniques that dramatically simplify and shorten the process of correct chip design by raising the level of abstraction on multiple dimensions without sacrificing final hardware quality.
Date of Conference: 3-7 Jan. 2006