Skip to Main Content
This tutorial discusses design challenges of scaled CMOS circuits in sub-90nm technologies and the design methodologies required to design them in order to produce robust designs with desired power performance trade-off. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines. On the technology front, the question arises whether we can continue along the traditional CMOS scaling path - reduce effective oxide thickness, improve channel mobility, and minimize parasitics. On the design front, researchers are exploring various circuit design techniques to deal with process variation, leakage and soft errors.