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Implementation of a high speed four transmitter space-time encoder using field programmable gate array and parallel digital signal processors

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2 Author(s)
P. J. Green ; Dept. of Electr. & Comput. Eng., Canterbury Univ., Christchurch, New Zealand ; D. P. Taylor

This paper describes the concept, architecture, development and demonstration of a high performance, 4 transmitter, real-time space time encoder designed for research into transmitter diversity and multiple input and multiple output (MIMO) wireless systems. It is implemented on a Xilinx Virtex 2 Pro field programmable gate array (FPGA) and parallel processing on multiple Freescale DSP56321 digital signal processors (DSP). The system is software defined to allow for flexibility in the choice of transmit modulation formats, data rates and space-time coding schemes. Hardware, firmware and software aspects of the space time encoder system to meet design requirements are discussed. The testing and demonstration of the system running the Alamouti space time coding scheme is covered

Published in:

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

Date of Conference:

17-19 Jan. 2006