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Address sequences for march tests to detect pattern sensitive faults

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2 Author(s)
B. Sokol ; Bialystok Tech. Univ., Poland ; S. V. Yarmolik

Proposed paper presents a methodology for RAM testing based on counter address sequences. Presented solution allows us to generate and obtain different address sequences for march tests and use them to detect Pattern Sensitive Faults with a very high probability. According to previous investigations, we can use march tests to test modern memory chips, because their transparent versions are very efficient for the faults testing and diagnoses. In this paper, the most important results were done to calculate the best distance between two consecutive address sequences and to find the most efficient method for Pattern Sensitive Faults detection with simple address sequences generation techniques.

Published in:

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

Date of Conference:

17-19 Jan. 2006