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A reconfigurable embedded decompressor for test compression

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3 Author(s)
Saiki, T. ; Graduate Sch. of Inf. Sci., Hiroshima City Univ., Japan ; Ichihara, H. ; Inoue, T.

Test compression/decompression methods for reducing the test application time and memory requirement of an LSI tester have been proposed. In these methods, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can compress highly the test data. However, these methods have some drawbacks, e.g., the coding algorithm may not be effective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to the used coding algorithms and a given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-re configurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding.

Published in:

Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on

Date of Conference:

17-19 Jan. 2006