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Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array

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2 Author(s)
Green, P.J. ; Dept. of Electr. & Comput. Eng., Canterbury Univ., Christchurch, New Zealand ; Taylor, D.P.

This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed.

Published in:

Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on

Date of Conference:

17-19 Jan. 2006

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