By Topic

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Vancaillie, L. ; Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium ; Kilchytska, Valeria ; Alvarado, J. ; Cerdeira, A.
more authors

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-Vth deep-submicrometer 0.12-μm silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25°C-220°C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.

Published in:

Electron Devices, IEEE Transactions on  (Volume:53 ,  Issue: 2 )