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Tiling parity-check matrix for reduced complexity high throughput low-density parity-check decoders

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2 Author(s)
Selvarathinam, A. ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; Gwan Choi

An approach for reducing hardware complexity of LDPC decoders is presented in this paper. Low-density parity-check (LDPC) codes have a sparse parity-check matrix (H matrix). In LDPC decoder, the H matrix is stored in memory and contains information about the parity check constraints. The approach presented in this paper constructs several sub-matrices (pseudo random patterns) that are repeatedly used to form the H matrix. The merits of this approach on the decoder architecture are two-fold. First, the switch logic associated with data forwarding in and out of the memory blocks, or alternately the routing of bit nodes to check nodes is simplified. Second, this approach reduces information stored in the design about the H matrix. Thus, the hardware complexity of the decoder is significantly reduced with an added advantage of increased throughput. LDPC code performance simulation results show that the proposed approach does not compromise the bit error rate performance (BER) compared to that of ideal/optimal H matrix for same code length (N = 2040) and rate.

Published in:

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

Date of Conference:

2-4 Nov. 2005