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Speedups from partitioning software kernels to FPGA hardware in embedded SoCs

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4 Author(s)
M. D. Galanis ; Dept. of Electr. & Comput. Eng., Patras Univ., Greece ; G. Dimitroulakos ; A. P. Kakarountas ; C. E. Goutis

This paper presents a hardware/software partitioning methodology for improving performance in single-chip systems comprised by processor and reconfigurable logic. The reconfigurable logic is realized by field programmable gate array technology. Critical software parts are selected for acceleration on the reconfigurable logic. A generic hybrid system-on-chip platform, which can model the majority of existing processor-FPGA systems, is considered by the method. The partitioning method uses an automated kernel identification process at the basic-block level for detecting critical software portions. Three different instances of the generic platform and two sets of benchmarks are used in the experiments. The analysis on five real-life applications showed that these applications spend an average of 69% of their instruction count in 11% on average of their code. The extensive experimentation illustrates that for the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For a platform composed by an 8-bit processor, the performance gains of eight DSP algorithms are considerably greater, since the average speedup equals 28.

Published in:

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

Date of Conference:

2-4 Nov. 2005