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Hardware implementation of an approximate string matching algorithm using bit parallel processing for text information retrieval systems

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2 Author(s)
Christophe Layer ; Dept. of Microelectronics, Ulm Univ., Germany ; Hans-Jorg Pfleiderer

As the increasing size of private or online electronic text collections reaches several terabytes, finding relevant information has become a real challenge for modern computerized systems. The low classification of the data stored in repositories exempted from quality control justifies the need for approximate matching methods maintaining the efficiency of the retrieval and accuracy of the results. Moreover, because the average bandwidth of the main memory is crucial for system performance, development of digital VLSI (very large scale integration) architectures for low-level and very high throughput data processing has been a main issue in this work. Thus this paper presents the hardware realization of a text search engine using bit-parallelism and a fast serial processing of the database information. It describes the internal architecture of an associative processor which was efficiently implemented and tested on an FPGA (field programmable gate array) platform, acting yet as an external hardware accelerator for standard PC solutions.

Published in:

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

Date of Conference:

2-4 Nov. 2005