Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Hardware implementation of an approximate string matching algorithm using bit parallel processing for text information retrieval systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Layer, C. ; Dept. of Microelectronics, Ulm Univ., Germany ; Pfleiderer, H.-J.

As the increasing size of private or online electronic text collections reaches several terabytes, finding relevant information has become a real challenge for modern computerized systems. The low classification of the data stored in repositories exempted from quality control justifies the need for approximate matching methods maintaining the efficiency of the retrieval and accuracy of the results. Moreover, because the average bandwidth of the main memory is crucial for system performance, development of digital VLSI (very large scale integration) architectures for low-level and very high throughput data processing has been a main issue in this work. Thus this paper presents the hardware realization of a text search engine using bit-parallelism and a fast serial processing of the database information. It describes the internal architecture of an associative processor which was efficiently implemented and tested on an FPGA (field programmable gate array) platform, acting yet as an external hardware accelerator for standard PC solutions.

Published in:

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

Date of Conference:

2-4 Nov. 2005