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A high-throughput area efficient FPGA implementation of AES-128 Encryption

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3 Author(s)
A. Brokalakis ; Dept. of Comput. Eng. & Inf., Patras Univ., Greece ; A. P. Kakarountas ; C. E. Goutis

Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94 Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.

Published in:

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

Date of Conference:

2-4 Nov. 2005