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The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using integer linear programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.