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A flexible multiplier for media processing

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4 Author(s)
Brunelli, C. ; Inst, of Digital & Comput. Syst., Tampere Univ. of Technol., Finland ; Salmela, P. ; Takala, J. ; Nurmi, J.

In the last years multimedia processing applications have gained more and more importance in the field of mobile and hand-held devices, requiring dedicated hardware platforms characterized by high performance computation capabilities with reduced area occupation and low power consumption. 2D graphics and signal processing applications in general benefit from the usage of integer single-instruction-multiple-data (SIMD) functional units, while 3D graphics applications can be significantly accelerated employing single precision floating-point functional units. This paper presents a model and implementation of a versatile multiplier able to perform either double precision, (paired) single precision floating-point multiplications or 16-bit or 8-bit SIMD integer (vector) multiplications; it was implemented on an FPGA device and compared to other floating-point multipliers and similar devices, each capable of performing only a limited subset of the proposed design. The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance; thus the proposed multiplier represents in particular a good candidate for usage in area-limited designs.

Published in:

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

Date of Conference:

2-4 Nov. 2005