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Hardware design for end-to-end modular exponentiation in redundant number representation

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2 Author(s)
Sanu, M.O. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Swartzlander, E.E.

In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed number representations. The major advantage of this algorithm over previously reported algorithms is that it does not require the result of each modular multiplication in the exponentiation process to be converted from the redundant representation back to a nonredundant form. In our algorithm, the conversion is only necessary at the end of all the modular multiplications. Avoiding the conversion speeds up the modular exponentiation process. In addition, the algorithm allows for a fast, modular, and scalable hardware implementation.

Published in:

Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on

Date of Conference:

2-4 Nov. 2005