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Systolic computational memory approach to high-speed codebook design

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3 Author(s)
K. Sano ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; C. Takagi ; T. Nakamura

This paper presents a systolic computational memory approach to high-speed codebook design required for vector quantization (VQ). Our proposed systolic computational memory has the advantages of both the systolic array and computational RAM: massively parallel processing capability and wide bandwidth of internal memory. By introducing deferred update of a codebook, the parallelism of the mini-max partial distortion competitive learning (MMPDCL) algorithm is enhanced and fully exploited by the proposed systolic computational memory for high-speed codebook design. The experiments of VQ-based image compression show that the FPGA-based prototype running at 33 MHz achieves about 400 times faster codebook design than a software approach on a general-purpose microprocessor running at 2 GHz

Published in:

Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005.

Date of Conference:

21-21 Dec. 2005