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The stretched-hypercube: a VLSI efficient network topology

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2 Author(s)
Shareghi, P. ; Sch. of Comput. Sci., Sharif Univ. of Technol., Tehran, Iran ; Sarbazi-Azad, H.

In this paper, we introduce a new class of interconnection networks for multiprocessor systems which we refer to as stretched-hypercubes, or shortly the stretched-cube networks. These networks are obtained by replacing an edge of the well-known hypercube network with an array of processors. Two interesting features of the proposed topology are its area-efficient VLSI layout and superior scalability over the traditional hypercube network. Some topological properties of the proposed network are studied. In addition, an area-efficient VLSI layout for the stretched-cube is suggested and some comparisons between the proposed network and previously studied networks such as the star and hypercube are conducted.

Published in:

Parallel Architectures,Algorithms and Networks, 2005. ISPAN 2005. Proceedings. 8th International Symposium on

Date of Conference:

7-9 Dec. 2005