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Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes

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4 Author(s)
Iyer, S. ; Univ. of Texas at Austin, TX ; Jain, J. ; Sahoo, D. ; Shimizu, T.

Formal verification, especially error detection, is rapidly increasing in importance with the rising complexity of designs. The main constraint in verification is the total amount of resources available - both time as well as memory. Most attempts at verification only use a single processor. Recently, various attempts have been made to use parallel and distributed methods for verification. However, verification in a Grid-based environment has not yet been very widely adopted. As personal computers gain in computing capacity, the concept of computation grids is gaining acceptance. Here, a grid is a network of machines that may not be dedicated to a specific computational use, but may only be available some of the time. This is a unique environment where massive parallelism is possible by using otherwise idle CPU cycles from a large number of computers. Such processors may even be in geographically diverse locations. We describe a Grid-based verifi- cation environment for detecting errors in a design. We verify user-written assertions as well as properties, e.g. unreachable code, index-out-of-range, that are extracted automatically from the design using a state-of-the-art HDL parser. Such an approach can help the user to quickly find RTL level bugs earlier in the design cycle.

Published in:

Test Symposium, 2005. Proceedings. 14th Asian

Date of Conference:

18-21 Dec. 2005