By Topic

Rapid prototyping of the sphere decoder for MIMO systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

The use of multiple input-multiple output (MIMO) technology is rapidly becoming the new frontier of wireless communication systems increasing their capacity and spectral efficiency. In order to validate this technology from an implementation point of view, field-programmable gate arrays (FPGAs), with their high level of parallelism, high densities and embedded multipliers, are a suitable platform for the study and prototyping of MIMO algorithms. This paper presents an FPGA implementation of the sphere decoder (SD) for MIMO detection. This algorithm provides optimal maximum likelihood (ML) performance with reduced complexity, compared to the maximum likelihood detector (MLD).

Published in:

DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on (Ref. No. 2005/11086)

Date of Conference:

19-20 Sept. 2005