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The use of multiple input-multiple output (MIMO) technology is rapidly becoming the new frontier of wireless communication systems increasing their capacity and spectral efficiency. In order to validate this technology from an implementation point of view, field-programmable gate arrays (FPGAs), with their high level of parallelism, high densities and embedded multipliers, are a suitable platform for the study and prototyping of MIMO algorithms. This paper presents an FPGA implementation of the sphere decoder (SD) for MIMO detection. This algorithm provides optimal maximum likelihood (ML) performance with reduced complexity, compared to the maximum likelihood detector (MLD).