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A new realization for multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing

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2 Author(s)
D. Raghuramireddy ; Lehrstuhl fuer Allgemeine & Theor. Elektrotech., Erlangen, Germany ; R. Unbehauen

An efficient multiprocessor implementation of 2D denominator-separable digital filters for real-time processing is presented. The realization is derived by minimizing the throughput delay and maximizing the parallelism using the basic primitive structure of M.Y. Dabbagh and W.E. Alexander (see ibid. vol.37, no.6, p.872-81, 1989). The proposed realization is as good and efficient as their realizations for the implementation of symmetric fan filters. It is shown that in special cases the proposed realization may be more efficient

Published in:

IEEE Transactions on Signal Processing  (Volume:40 ,  Issue: 9 )