Performance-timing overhead trade-off analysis for a low-power data bus encoding based on input lines reordering

This paper analyzes the performance and timing overhead trade-off for a recently proposed data bus encoding scheme for low-power based on data lines reordering. The bus switch (BS) mechanism introduces greater activity savings than previous approaches; the hardware complexity of the encoder suggests to apply BS in off-chip buses, where the parasitic capacitance makes dynamic power dissipation in the bus lines the dominant contribution to power consumption. In the basic BS implementation, the encoding circuits included extra bus lines which degrade the energy saving. This paper illustrates and analyzes a circuit implementation with only one extra line, at the cost of a small time overhead. This solution strongly enhances the advantage in off-chip communications, where the available number of pads represents a key resource in low-cost packages. Our results indicate that the effectiveness of the approach strongly depend on an a-priori traffic analysis.