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Digitally controlled DC-DC converters are affected by quantization effects on A/D converters and digital pulse-width modulators (DPWMs) which may result in undesirable limit-cycle oscillations. Existing static and dynamic models predict the existence of only a small part of limit cycle oscillations, so that extensive time-domain simulations are usually needed in order to verify the presence of limit-cycle oscillations under different load and input voltage conditions. This paper proposes an alternative approach based on statistical models. Modelling the quantization error as a white noise, including the quantization effects on the controller and converter state variables, and evaluating the correlation between state variables, a statistical prediction of limit-cycle oscillations is obtained. By means of the proposed method, design criteria for the regulator parameters, in terms of achievable bandwidth, location of PID zeros and desired phase margin, can be derived. Simulation and experimental results confirm the validity of the proposed method.