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Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations. Part I

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2 Author(s)
Xin Wu ; Ansoft Corp., Pittsburgh, PA, USA ; Monti, A.

In this paper, the interfacing schemes for power-hardware-in-the-loop (PHIL) simulations are studied. In Part I, different simulation/hardware interfaces are introduced, and a novel interfacing scheme based on the time-variant first-order approximation of dynamics of the hardware under test (HUT) is proposed. The performances of different interfaces are compared through the decoupled simulation of first-order systems. More advanced performance evaluation methods are introduced in part II.

Published in:

Industrial Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE

Date of Conference:

6-10 Nov. 2005