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Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model

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3 Author(s)
Che-Hua Shih ; Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan ; Juinn-Dar Huang ; Jing-Yang Jou

Verifying if an integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the nondeterministic extended finite state machine (NEFSM), and then propose an automatic stimulus generation approach based on the NEFSM. This approach is capable of providing numerous biasing options. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.

Published in:

High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International

Date of Conference:

30 Nov.-2 Dec. 2005