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A 90nm power optimization methodology and its' application to the ARM 1136SF-S microprocessor

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19 Author(s)
Khan, A. ; Cadence Design Syst., Inc., San Jose, CA ; Watson, P. ; Kuo, G. ; Le, D.
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An electrical and physical design power optimization methodology and design techniques developed to create an ARM 1136SF-S microprocessor in 9Onm standard CMOS are presented. A 40% reduction in power dissipation has been achieved while maintaining a 355 MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon

Published in:

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Date of Conference:

21-21 Sept. 2005