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Design of a CMOS floating-gate resistor for highly linear amplifier and multiplier applications

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2 Author(s)
Ozalevli, E. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA ; Hasler, P.

We present implementations of highly linear amplifier and multiplier circuits that employ a linear CMOS resistor. This tunable resistor is built by utilizing the common-mode linearization technique, and by exploiting the gate-coupling and charge-storage characteristics of the floating-gate transistors. It exhibits 0.01% THD for 1Vpp input. Also, the amplifier has an input linear range of 2.5Vpp for differential and single-ended inputs, and achieves 0.018% THD for 1Vpp differential input

Published in:

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Date of Conference:

21-21 Sept. 2005

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