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The 180MSPS, 13b CMOS pipelined ADC of a transceiver is implemented without a dedicated track-and-hold stage and utilizes a front-end 2.5b stage with matched MDAC/comparator tracking circuits. The ADC demonstrates ENOB of 10.6b at 15MHz and 9.7b at 100MHz. It employs a low-jitter delay-lock loop for its phasing. The dual I/Q 12b 180MSPS DACs show over 62dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.