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Using cache to reduce power in content-addressable memories (CAMs)

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2 Author(s)
Pagiamtzis, K. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. ; Sheikholeslami, A.

We propose using caching to save power in content-addressable memories (CAMs). By using a small cache along with the CAM, we avoid accessing the larger and higher power CAM. For a cache hit rate of 90%, the cache-CAM (C-CAM) saves 80% power over a conventional CAM, for a cost of 15% increase in silicon area. Even at a low hit rate of 50%, a power savings of 40% is achieved. The proposed C-CAM is employed in the design of a testchip demonstrating a 2.6 fJ/bit/search in a 0.18 mum CMOS process

Published in:

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Date of Conference:

21-21 Sept. 2005