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Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

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17 Author(s)
Beacom, T. ; Syst. & Technol. Group, IBM Rochester, NY, USA ; Buchholtz, T. ; Bradley, D. ; Randolph, J.
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This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm2 in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68°C.

Published in:

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Date of Conference:

18-21 Sept. 2005