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A 0.14mW/Gbps high-density capacitive interface for 3D system integration

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6 Author(s)
Fazzi, A. ; Adv. Res. Center on Electron. Syst., Bologna Univ., Italy ; Magagni, L. ; Mirandola, M. ; Canegallo, R.
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This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8×8μm2 enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.

Published in:

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Date of Conference:

18-21 Sept. 2005

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