Designing an FPGA SoC using a standardized IP block interface

Designing systems on-chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of processing elements (PEs) that use different communication protocols and interfaces complicates the system-level design methodology. Recent work provided a proof of concept demonstrating how a controller could be used to provide a generic system-level interface that separates the functionality of a PE from its communication protocols and makes the actual physical interconnections between modules a lesser problem. This paper summarizes how the SIMPPL model is able to implement the system-specific requirements of an MPEG-1 video decoder and the overhead this framework incurs.