A scaleable FFT/IFFT kernel for communication systems using codesign approach

This paper presents a new architecture of scaleable FFT processor using hardware/software codesign technique for orthogonal frequency division multiplexing (OFDM) systems. The architecture uses a radix-4 butterfly node located on both hardware and software processing elements. We employ an in-place memory strategy, resulting that the butterfly inputs and outputs can be stored at the same memory location without conflict. The memory is partitioned into 4 banks for pipelined computation. To demonstrate the codesign concept, a 256-point FFT/IFFT engine is completed in a Xilinx Vertex-II Pro FPGA chip that contains PowerPC processor where the hardware is modeled by VHDL and the software is written in C. The proposed architecture achieves 256-point FFT in 10.56 ps , 64-point in 2.16 mus and 16-point in 480 ns, making it viable for today's demanding OFDM applications