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FPGA organization for the fast path-based neural branch predictor

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3 Author(s)
O. Cadenas ; Sch. of Syst. Eng., Reading Univ., UK ; G. Megson ; D. Jones

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor. Our results suggest that practical sizes of prediction tables are limited to around 32KB to 64KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However, the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Published in:

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Date of Conference:

11-14 Dec. 2005