By Topic

A single-chip FPGA implementation of real-time adaptive background model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
K. Appiah ; Dept. of Comput. & Informatics, Lincoln Univ., UK ; A. Hunter

This paper demonstrates the use of a single chip FPGA for the extraction of highly accurate background models in real time. The models are based on 24 bit RGB values and 8 bit grayscale intensity values. Three background models are presented, all using a camcorder, single FPGA chip, four blocks of RAM and a display unit. The architectures have been implemented and tested using a Panasonic NV-DS60B digital video camera connected to a Celoxica RC300 prototyping platform with a Xilinx Virtex II XC2v6000 FPGA and 4 banks of onboard RAM. The novel FPGA architecture presented has the advantages of minimizing latency and the movement of large datasets, by conducting time critical processes on BlockRAM. The systems operate at clock rates ranging from 57MHz to 65MHz and are capable of performing preprocessing functions like temporal low pass filtering on standard frame size of 640 times 480 pixels at up to 210 frames per second

Published in:

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Date of Conference:

11-14 Dec. 2005