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A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors

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2 Author(s)
Xiaofang Wang ; Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA ; S. G. Ziavras

Encouraged by continuous advances in FPGA technologies, we explore high performance multi-processor-on-a-programmable-chip (MPoPC) reconfigurable architectures. This paper proposes a methodology for assigning resources at run time and scheduling large scale floating point, data parallel applications on our mixed mode HERA MPoPC. HERA stands for heterogeneous reconfigurable architecture. An application is represented by a novel mixed mode task flow graph which is scheduled to run under a variety of independent or cooperating parallel computing modes: SIMD (single instruction, multiple data), multiple SIMD and MIMD (multiple instruction, multiple data). The reconfigurable logic is customized at static time and reconfigured at run time to match application characteristics. An in-house developed parallel power flow analysis code by Newton's method is employed to verify the methodology and evaluate the performance. This application is of utmost importance to any power grid

Published in:

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Date of Conference:

11-14 Dec. 2005