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VLSI implementation of two-dimensional DCT processor in real time for video codec

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3 Author(s)
P. C. Jain ; Central Electron. Eng. Res. Inst., Pilani, India ; W. Schlenk ; M. Riegel

A new VLSI circuit for computing the two-dimensional discrete cosine transform (2D-DCT) using the Philips fast computational algorithm for a video codec in real time has been designed and tested using 1-μm CMOS standard cell technology. This processor requires a minimum number of arithmetic components and satisfies the CCITT standards using a minimum possible number of bits for cosine coefficients and internal word length compared to other architectures. The architecture is so flexible that it can be used for inverse DCT processing just by changing the control signals. The architecture works in real time at a 32-MHz rate. The processor can be used for still picture and motion video compression. Due to its high-speed processing capability it can be used in video codecs at different bit rates

Published in:

IEEE Transactions on Consumer Electronics  (Volume:38 ,  Issue: 3 )