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The asymmetrical half-bridge (AHB) topology discussed in this paper is one of the complementary driven pulse-width modulated converter topologies, which presents an inherent zero-voltage switching (ZVS) capability. In the previous work, the ideal operation of the converter and the ZVS realization process have been analyzed. However, the influence of the circuit parasitics on the output voltage drop and the design constraints of the circuit parameters to ensure the ZVS operation have not been investigated. The minimum load needed to ensure the ZVS operation is also not readily available. This paper presents a detailed and practical design for a 1-MHz AHB converter. A revised voltage transfer ratio of the converter is derived considering the influence of circuit parasitics and the ZVS transition. Two circuit parameters responsible for maintaining the ZVS operation are the transformer leakage inductance and the interlock delay time between the gate signals of two switches. A design method of the two parameters is proposed, which can ensure the ZVS transition. The possible ZVS range of the load variation is also investigated. A 50-W AHB converter with 1-MHz switching frequency was constructed, and a maximum efficiency of 91% was achieved.