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Testing embedded sequential cores in parallel using spectrum-based BIST

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2 Author(s)
Xiaoding Chen ; Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA ; Hsiao, M.S.

We present a new BIST (built-in-self-test) architecture for system-on-a-chip (SOC), which can test a cluster of embedded sequential cores simultaneously. The compressed spectrum for a cluster of cores under test is computed by performing spectral analysis individually on all cores. Because there is no need to combine the cores to extract the spectrum for the entire cluster, the computation complexity is greatly reduced. For each individual core, we propose an interleaved state relaxation on the compacted test sequence for its characteristic fault set, leading to a partially specified, interleaved sequence which can be merged in a much easier way. A delay network and a switching network are added selectively to allow for more aggressive merging of spectra. Experimental results show that the same level of fault coverage can be achieved for each individual core with negligible hardware overhead, while the test application time for testing the entire cluster can be reduced by up to four times and the test data storage requirement is reduced by up to 42 percent.

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Computers, IEEE Transactions on  (Volume:55 ,  Issue: 2 )