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Power-efficient error tolerance in chip multiprocessors

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4 Author(s)
Rashid, M.W. ; Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA ; Tan, E.J. ; Huang, M.C. ; Albonesi, D.H.

The microprocessor industry is rapidly moving to the use of multicore chips as general-purpose processors. Whereas the current generation of chip multiprocessors (CMPs) target server applications, future desktop processors likely have tens of multithreaded cores on a single die. Various redundant multithreading (RMT) approaches exploit the multithreaded capability of current general-purpose microprocessors. These approaches replicate the entire program, running it as a separate thread using time or space redundancy. This guards the processor core against all errors, including those in combinational logic. Because RMT exploits the existing multithreaded hardware, it requires only a modest amount of additional hardware support for comparing results and, depending on the implementation, duplicating inputs.

Published in:

Micro, IEEE  (Volume:25 ,  Issue: 6 )