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Hf-profile engineered HfSiON gate dielectrics for 65nm LSTP CMOS

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7 Author(s)
Inoue, M. ; Wafer Process Eng. Dev. Div., Renesas Technol. Corp., Hyogo, Japan ; Mizutani, M. ; Nomura, K. ; Yugami, J.
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Gate dielectric as thin as E0T=1.6nm or below is required for 65nm CMOS devices according to ITRS (2003). High-k materials such as HfSiON with satisfactory low leakage are expected as an alternative gate dielectric. However, two big problems have been revealed in the use of HfSiON gate dielectric; (i) Reduction of effective carrier mobility (μeff) in scaled EOTs and (ii) high K, in pFETs as stated in C. Hobbs et al. (2003) and L.-A. Ragnarsson et al. (2003). Here, we propose Hf-profile engineering; higher Hf concentration near the gate electrode and lower near the substrate for improving degraded μeff. Combination of metal-Hf PVD on interface layer (IL) with precise thickness control and post oxidation is a suitable technique to form such Hf-profile engineered HfSiON (HPE-HfSiON) films. In order to lower K, in pFETs, we present forward-bias technique as presented in M. Miyazaki et al. (2002).

Published in:

Future of Electron Devices, 2004. International Meeting for

Date of Conference:

26-28 July 2004

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