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Low latency time CORDIC algorithms

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3 Author(s)
Timmermann, D. ; Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisburg, Germany ; Hahn, H. ; Hosticka, Bedrich J.

Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described

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Computers, IEEE Transactions on  (Volume:41 ,  Issue: 8 )