Referenced Items are not available for this document.
This paper describes a method of IC layout verification on manufacturability. The method considers matches between results of lithography modeling and a image on a wafer obtained after manufacturing
Published in:
Microwave & Telecommunication Technology, 2005 15th International Crimean Conference
(Volume:2
)
Date of Conference: 16-16 Sept. 2005
- Page(s):
- 455 - 456 Vol. 2
- Print ISBN:
- 966-7968-80-4
- INSPEC Accession Number:
- 9004290
- Conference Location :
- Sevastopol, Crimea
- Digital Object Identifier :
- 10.1109/CRMICO.2005.1564989
- Product Type:
- Conference Publications
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