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IC layout verification method, which considers mismatches between results of lithographical modeling and a real image

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4 Author(s)
S. N. Koukharenko ; Belarusian State Univ. of Informatics & Radioelectron., Minsk, Belarus ; S. V. Volk ; A. M. Zayats ; A. G. Smimov

This paper describes a method of IC layout verification on manufacturability. The method considers matches between results of lithography modeling and a image on a wafer obtained after manufacturing

Published in:

2005 15th International Crimean Conference Microwave & Telecommunication Technology  (Volume:2 )

Date of Conference:

16-16 Sept. 2005