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Design and Development of Interconnects for Ultra-Fine Pitch Wafer Level Packages

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3 Author(s)
A. A. O. Tay ; Nano/Microsystems Integration Laboratory, National University of Singapore Email: ; M. K. Iyer ; R. R. Tummala

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 mum by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10Gbps, while guaranteeing thermo-mechanical reliability and lowering the cost. The above requirements are challenging, needing innovative interconnection designs. This paper describes the development of interconnection schemes for wafer level packages of 100 mum pitch, involving rigid, compliant and semi-compliant interconnection technologies. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections in respect of electrical performance and thermo-mechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermo-mechanical reliability and the final "optimum" design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower

Published in:

2005 6th International Conference on Electronic Packaging Technology

Date of Conference:

2-2 Sept. 2005