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A sub-10-ps multiphase sampling system using redundancy

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3 Author(s)
Li-Min Lee ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Weinlader, D. ; Yang, C.-K.K.

This paper demonstrates a multichannel multiphase sampling system using a 700-MHz operating frequency to produce a base sampling rate of 7 GSample/s for each channel in a typical 0.18-μm CMOS technology. An extra phase cluster with <10-ps sampling phase spacing is generated. To achieve this small phase spacing, static phase and voltage errors are digitally calibrated. Additionally, a redundancy technique is introduced in this paper to further halve the residual voltage error of the samplers. A third technique, i.e., "reference subtraction," is applied to remove cross-channel correlated dynamic noise. The resulting phase spacing is only limited by the uncorrelated random noise in the system. With this fine sampling phase resolution, this system has the ability to measure cycle-to-cycle jitter in real time.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 1 )

Date of Publication:

Jan. 2006

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