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A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

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7 Author(s)
Hsu, S.K. ; Circuits Res. Labs., Intel Corp., Hillsboro, OR, USA ; Mathew, S.K. ; Anders, M.A. ; Zeydel, B.R.
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This paper describes a 16 × 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-Vt CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50°C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm2 while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 μW and high noise tolerance with all high-Vt usage; 3) ultra low standby-mode power of 75 μW and fast wake-up time of <1 cycle using PMOS sleep transistors; 4) scalable multiplier performance up to 1.5 GHz, 32 mW measured at 1.95 V, 50°C, and (v) low-voltage mode multiplier performance of 50 MHz, 79μW measured at 570 mV, 50°C.

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 1 )