By Topic

The Parity protected, multithreaded register files on the 90-nm itanium microprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
E. S. Fetzer ; Intel Corp., Fort Collins, CO, USA ; D. Dahle ; C. Little ; K. Safford

The integer and floating-point register files of the 90-nm generation Itanium Microprocessor are described. A pulsed, shared word line technique enables a 22 ported integer array with only 12 word lines per register. An in-register ripple parity system provides soft error detection with no impact to operand bypass or pipeline depth while keeping consuming less that 6% of the total register datapath area. The register file implements temporal multi-threading by multiplexing the read and write ports to two storage nodes enabling registers to write both foreground and background threads to the same register at the same time. Thread switching completes in one cycle. The register files are fabricated in a 7-layer 90-nm process and operate up to 2.0 GHz while consuming 400 mW per register array.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 1 )