Referenced Items are not available for this document.
Local voltage dithering provides near optimum savings when workload varies for fine-grained blocks. Combining this approach with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90-nm test chip. Operating at 330 mV provides minimum energy per cycle at 9× less energy than ideal shutdown for reduced performance scenarios. Measurements from the test chip characterize the impact of temperature on the minimum energy point.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
1
)
Date of Publication: Jan. 2006
- Page(s):
- 238 - 245
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8710519
- Digital Object Identifier :
- 10.1109/JSSC.2005.859886
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 December 2005
- Issue Date :
- Jan. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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